SH7764 Datasheet, PDF (790/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 19 Ethernet Controller (EtherC)
19.3.26 Broadcast Frame Receive Count Setting Register (BCFRR)
BCFRR is used to set the number of Broadcast frames that can be received continuously.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BCF[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 16 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
15 to 0 BCF[15:0] All 0 R/W Receive Count for Continuous Broadcast Frames
The DA can receive a Broadcast address frame up to
the number of times set in these bits. If the reception is
performed for more times than the set value, the excess
Broadcast frames are discarded.
H’0000: No limitation for receive count
H’0001: 1 frame can be received
:
:
H'FFFF: 65,535 continuous frames can be received
Rev. 1.00 Nov. 22, 2007 Page 734 of 1692
REJ09B0360-0100