SH7764 Datasheet, PDF (419/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
Channel Name
Abbrev. R/W P4 Address
Area 7 Address Access Size*³
0
DMA source address register B0
SARB0 R/W H'FF60 8120
H'1F60 8120
32
DMA destination address register B0 DARB0 R/W H'FF60 8124
H'1F60 8124
32
DMA transfer count register B0
TCRB0 R/W H'FF60 8128
H'1F60 8128
32
1
DMA source address register B1
SARB1 R/W H'FF60 8130
H'1F60 8130
32
DMA destination address register B1 DARB1 R/W H'FF60 8134
H'1F60 8134
32
DMA transfer count register B1
TCRB1 R/W H'FF60 8138
H'1F60 8138
32
2
DMA source address register B2
SARB2 R/W H'FF60 8140
H'1F60 8140
32
DMA destination address register B2 DARB2 R/W H'FF60 8144
H'1F60 8144
32
DMA transfer count register B2
TCRB2 R/W H'FF60 8148
H'1F60 8148
32
3
DMA source address register B3
SARB3 R/W H'FF60 8150
H'1F60 8150
32
DMA destination address register B3 DARB3 R/W H'FF60 8154
H'1F60 8154
32
DMA transfer count register B3
TCRB3 R/W H'FF60 8158
H'1F60 8158
32
0, 1
DMA extended resource selector 0 DMARS0 R/W H'FF60 9000
H'1F60 9000
16
2, 3
DMA extended resource selector 1 DMARS1 R/W H'FF60 9004
H'1F60 9004
16
4, 5
Note:
DMA extended resource selector 2 DMARS2 R/W H'FF60 9008
H'1F60 9008
16
1. Writing 0 after read 1 of HE or TE bit of CHCR is possible to clear the flag.
2. Writing 0 after read 1 of AE or NMIF bit of DMAOR is possible to clear the flag.
3. Accessing with other access sizes is prohibited.
Rev. 1.00 Nov. 22, 2007 Page 363 of 1692
REJ09B0360-0100