SH7764 Datasheet, PDF (726/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Bit
6 to 4
3
2
1
0
Initial
Bit Name Value R/W Description
CKDV[2:0] 000
R/W Serial Oversampling Clock Division Ratio
These bits define the division ratio between
oversampling clock AUDIO_CKL[5:0] and the serial bit
clock.
These bits are ignored if SCKD = 0.
The serial bit clock is used for the shift register and is
provided from the SSISCK[5:0] pin.
000: Serial bit clock frequency = oversampling clock
frequency/1
001: Serial bit clock frequency = oversampling clock
frequency/2
010: Serial bit clock frequency = oversampling clock
frequency/4
011: Serial bit clock frequency = oversampling clock
frequency/8
100: Serial bit clock frequency = oversampling clock
frequency/16
101: Serial bit clock frequency = oversampling clock
frequency/6
110: Serial bit clock frequency = oversampling clock
frequency/12
111: Setting prohibited
MUEN
0
R/W Mute Enable
0: SSI_CH0 to SSI_CH5 are not muted.
1: SSI_CH0 to SSI_CH5 are muted.

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
TRMD
0
R/W Transmit/Receive Mode Selection
0: SSI_CH0 to SSI_CH5 are in receive mode.
1: SSI_CH0 to SSI_CH5 are in transmit mode.
EN
0
R/W Operation Enable
0: SSI_CH0 to SSI_CH5 operation is disabled.
1: SSI_CH0 to SSI_CH5 operation is enabled.
Rev. 1.00 Nov. 22, 2007 Page 670 of 1692
REJ09B0360-0100