SH7764 Datasheet, PDF (1381/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 Sampling Rate Converter (SRC)
26.2.5 SRC Control Register (SRCCTRL)
SRCCTRL is a 16-bit readable/writable register that enables/disables the SRC module operation,
enables/disables the interrupt requests, and specifies flush processing, clear processing of the
internal work memory, and the input and output sampling rates.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
-
-
- SRCEN -
EEN FL
CL
IFS[3:0]
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R/W R R/W R/W R/W R/W R/W R/W R/W R
2
1
0
-
OFS [1:0]
0
0
0
R R/W R/W
Initial
Bit
Bit Name Value R/W Description
15 to 13 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
12
SRCEN
0
R/W SRC Module Enable
Enables/disables the SRC module operation.
0: Disables the SRC module operation.
1: Enables the SRC module operation.
Note: When the SRCEN bit is 1, do not modify the
following bits:
Register Name Bit
Bit Name
SRCIDCTRL
9
IED
SRCODCTRL
9, 10
OCH, OED
SRCCTRL
7 to 4, 0 IFS[3:0], OFS
11

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 1325 of 1692
REJ09B0360-0100