SH7764 Datasheet, PDF (1246/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 G2D
Register Hardware Software
Data
abbrev.
reset reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GTRCR
Y
Y0
0
MTRAR
N
N * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ** *
MTRBR
N
MTRCR
N
N ********************************
N ********************************
MTRDR
N
N ********************************
MTRER
N
N ********************************
MTRFR
N
N ********************************
MTRGR
N
N ********************************
MTRHR
N
N ********************************
MTRIR
N
N ********************************
GTROFSXR N
N
****************
GTROFSYR N
N
****************
ZCLPMIN N
ZCLPMAX N
N ********************************
N ********************************
ZSATVMINR N
N ********************************
[Legend]
* _{: Undefined value. Value is retained at a hardware reset and software reset.}
0 _{: Initialized to 0 at a hardware reset and software reset.}
1 _{: Initialized to 1 at a hardware reset.}
: Reserved. This bit is always read as 0. The write value should always be 0.
* : Reserved. Value is retained at a hardware reset and software reset. The read value is undefined. The write value should always be 0.
0 _{: Reserved. Initialized to 0 at a hardware reset and software reset. The write value should always be 0.}
1 _{: Reserved. Initialized to 1 at a hardware reset and software reset. The write value should always be 1.}
23.3.1 System Control Registers
(1) System Control Register (SCLR)
Offset:
H'000
Initial Value: H'80000000
The system control register (SCLR) is a 32-bit readable/writable register that specifies system
operation.
SCLR is initialized as follows at a hardware reset:
• Bit SRES is set to 1.
• Bit RS is cleared to 0.
Setting both the SRES and RS bits to 1 simultaneously is prohibited.
Rev. 1.00 Nov. 22, 2007 Page 1190 of 1692
REJ09B0360-0100