SH7764 Datasheet, PDF (493/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
Initial
Bit
Bit Name Value
15
SSI_ACH 0
0
14
SSI_ADM 0
A0
13
G2D
0
12 to 9 —
All 0
8
DMAC 0
7
H-UDI 0
6
—
0
5
WDT
0
4
SCIF1 0
3
SCIF0 0
2
—
0
1
TMU1 0
0
TMU0 0
R/W Function
Description
R
Indicates SSI_A (SSICH0)
interrupt source
Indicates interrupt
sources for each
R
Indicates SSI_A (SSIDMA0)
interrupt source
peripheral module
(INT2A1 is affected by
the state of the
R
Indicates G2D interrupt source _{interrupt mask}
R
Reserved
register).
These bits are always read as 0. ^{0: No interrupts}
R
Indicates interrupt source
1: Interrupts are
generated
R
Indicates H-UDI interrupt source
Note: Reading the
R
Reserved
INTEVT code
This bit is always read as 0.
notified to the
R
Indicates WDT interrupt source
CPU directly
can identify
R
Indicates SCIF1 interrupt source
interrupt
R
Indicates SCIF0 interrupt source
R
Reserved
This bit is always read as 0.
sources. In this
case, reading
INT2A1 is not
necessary.
R
Indicates TMU1 interrupt source
R
Indicates TMU0 interrupt source
Rev. 1.00 Nov. 22, 2007 Page 437 of 1692
REJ09B0360-0100