SH7764 Datasheet, PDF (406/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
(c) WAW (Write after Write)
The case should be taken into consideration in which a write access overwrites the data that is
written by the write access subsequent to the write access. In other words, while a write request
from a module is suspended on the bus, data may be written by another module, and then the
suspended write may be reflected. This case, where data is written to the same address
consecutively, can be managed through software or system. However, it should be guaranteed that
the preceding write access has been reflected on the memory prior to the subsequent write access.
(d) RAW (Read after Write)
The case should be taken into consideration in which a preceding write is not reflected on the
subsequent read data. In other words, while a write request from a module is suspended on the
bus, data may be read by another module, and then the suspended write may be reflected. This
case, where data is written to the same address consecutively, can be managed through software or
system. However, it should be guaranteed that the preceding write access has been reflected on the
memory prior to the subsequent read access.
From (a) to (d), some measures should be taken to check if a write access has been reflected on the
memory, which is described in the following sections.
(2) Confirming Reflection of Write Access
(a) Write Access by SuperHyway Bus Devices
Execute the SYNCO instruction by the CPU to confirm that the write data has been reflected on
the memory. This guarantees that the write data having been stored in the SuperHyway bus
interface (SHIF) in the MCU has been reflected on the memory. An example is given below in
which the CPU writes the display list to the main memory and instructs the 2D graphics engine to
start rendering (figure 11.24). Note that no coherency-related problems occur when the CPU alone
accesses the memory consecutively.
1. The CPU writes the display list (last write), and then executes the SYNCO instruction. The
CPU stops until the ack signal is returned from the SuperHyway bus.
2. The SuperHyway bus interface (SHIF) in the MCU accepts the write data from the
SuperHyway bus. At this point, the ack signal is not returned to the SuperHyway bus device.
3. The SHIF outputs the write data to the arbiter (ARBT).
4. At the same cycle as the step 3, the ARBT carries out arbitration. When the SHIF acquires the
bus mastership as a result of arbitration, the ARBT returns the acceptance signal (fin).
5. The ARBT outputs the write data to the SBSC at the next cycle.
6. When data is accepted by the ARBT, the SHIF returns the response signal to the SuperHyway
bus device.
Rev. 1.00 Nov. 22, 2007 Page 350 of 1692
REJ09B0360-0100