SH7764 Datasheet, PDF (707/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
18.3.9 Block Count Source Registers 0 to 5 (SSIBLCNTSR0 to SSIBLCNTSR5)
SSIBLCNTSR0 to SSIBLCNTSR5 is a 32-bit readable/writable register that set the transfer byte
count as SSIBLCNT0 to SSIBLCNT5 increment timing other than the port function. This register
value is initialized when either of the conditions is implemented such as hardware reset, software
reset or software reset for SSI_DMAC (DMRST bit in SSIDMACOR0 to SSIDMACOR3). To be
written to this register, DMEN bit in SSIDMCOR0 to SSDMCOR5 must be 0.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLCNTSR[31:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
BLCNTSR[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 0 BLCNTSR All 0
[31:0]
R/W SSIBLCNT0 to SSIBLCNT5 Increment Timing
These bits set the transfer byte count as SSIBLCNT0 to
SSIBLCNT5 increment timing.
The following transfer count should be selected
according to the RDMA or WDMA maximum burst size.
1 burst: 8 × n [H'08 × n] (bytes)
2 bursts: 16 × n [H'10 × n] (bytes)
4 bursts: 32 × n [H'20 × n] (bytes)
Rev. 1.00 Nov. 22, 2007 Page 651 of 1692
REJ09B0360-0100