SH7764 Datasheet, PDF (816/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name Value R/W Description
21
TC
0
R/W Frame Transmit Complete
Indicates that all the data specified by the transmit
descriptor has been transmitted from the EtherC. This
bit is set to 1, assuming the completion of transmission,
when transmission of one frame is completed in single-
frame/single-buffer operation or when the last data of a
frame has been transmitted and the transmit descriptor
valid bit (TACT) of the next descriptor is not set in for
the processing of multi-buffer frame. After frame
transmission, the E-DMAC writes the transmission
status back to the relevant descriptor.
0: Transfer not complete, or no transfer directive
1: Transfer complete
20
TDE
0
R/W Transmit Descriptor Empty
Indicates that the transmit descriptor valid bit (TACT) of
a transmit descriptor read by the E-DMAC is not set if
the previous descriptor does not represent the end of a
frame in multi-buffer frame processing based on single-
frame/multi-descriptor operation. As a result, an
incomplete frame may be sent.
0: Transmit descriptor active bit TACT = 1 detected
1: Transmit descriptor active bit TACT = 0 detected
When transmit descriptor empty (TDE = 1) occurs,
execute a software reset and initiate transmission. In
this case, transmission starts from the address that is
stored in the transmit descriptor list start address
register (TDLAR).
19
TFUF
0
R/W Transmit FIFO Underflow
Indicates that an underflow has occurred in the transmit
FIFO during frame transmission. Incomplete data is
sent onto the line.
0: Underflow has not occurred
1: Underflow has occurred
Rev. 1.00 Nov. 22, 2007 Page 760 of 1692
REJ09B0360-0100