SH7764 Datasheet, PDF (727/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
18.3.17 Status Registers 0 to 5 (SSISR0 to SSISR5)
SSISR0 to SSISR5 are configured by status flags that indicate the operating status of SSI_CH0 to
SSI_CH5 and bits that indicate the current channel number and word number.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


 DMRQ UIRQ OIRQ IIRQ DIRQ 







Initial value: 0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
R/W: R R R R R/W* R/W* R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0











 CHNO[1:0] SWNO IDST
Initial value: 1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
R/W: R R R R R R R R R R R R R R R R
Initial
Bit
Bit Name Value R/W Description
31 to 29 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
28
DMRQ 0
R
DMA Request Status Flag
This status flag allows the CPU to see the status of the
DMA request from SSI_CH0 to SSI_CH5 modules.
• TRMD = 0 (Receive mode)
If DMRQ = 1, SSIRDR0 to SSIRDR5 have unread
data.
If SSIRDR0 to SSIRDR5 are read, then DMRQ = 0
until the SSIRDR0 to SSIRDR5 receive new unread
data
• TRMD = 1 (Transmit mode)
If DMRQ = 1, the SSIRDR0 to SSIRDR5 request
data to be written to continue the data transmission
on the audio serial bus.
Once data is written to SSITDR0 to SSITDR5, then
DMRQ = 0 until further transmit data is requested.
Rev. 1.00 Nov. 22, 2007 Page 671 of 1692
REJ09B0360-0100