SH7764 Datasheet, PDF (734/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
18.4 Operation
18.4.1 Operation of SSI_CLKSEL
The SSI_CLKSEL connects the audio clock and serial-bit clock or serial-word select signal, which
are input from the SSI interface for each channel, to SSI_CH0 through SSI_CH5 depending on
register settings.
• Selecting audio clock
The audio clock for SSI_CH0 to SSI_CH5 (AUDIO_CLK[5:0]) is selected by the
SSI_CLKSEL according to the SCKS[2:0] bits in SSIDMCOR0 to SSIDMCOR5.
In the initial state, the audio clock of the same channel is selected, such as AUDIO_CLK0 =
SSI_CH0.
• Selecting serial bit clock or serial word select signal
The serial bit clock or serial word select signal for SSI_CH0 to SSI_CH5
(SSISCK[5:0]/SSIWS[5:0]) is selected by the SSI_CLKSEL according to the SCKSIP[2:0] or
SCKOP[2:0] bits in SSIDMCOR0 to SSIDMCOR5.
In the initial state, the serial bit clock or serial word select signal of the same channel is
selected, such as SSISCK0 = SSI_CH0.
18.4.2 Operation of SSI_DMAC0 and SSI_DMAC1
The SSI_DMAC0 and SSI_DMAC1 perform data transfer between six SSI channels (SSI_CH0 to
SSI_CH5) and external memory or on-chip memory.
The SSI_DMAC0 and SSI_DMAC1 provide the transmit and receive FIFO buffers (32 bits × 16
stages), which enable high-speed continuous communication effectively.
The SSI_DMAC0 and SSI_DMAC1 counts transferred data in any block units. This effectively
controls interrupt generation or data transfer including data transfer suspension in block units.
During data transfer suspension, the sound can pause by sending arbitrary data (for example, silent
data) continuously to SSI_CH0 through SSI_CH5.
Rev. 1.00 Nov. 22, 2007 Page 678 of 1692
REJ09B0360-0100