SH7764 Datasheet, PDF (1275/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 G2D
the IEEE 754 standard. Since the setting is compared with the W value, set a value corresponding
to W in ZSATVMINR.
Since internal computation is carried out with 32-bit fixed-point operations (16-bit integer portion
and 16-bit fractional portion), ZSATVMINR should be set within the range of 2^−16 ≤
ZSATVMINR ≤ ZCLPMINR ≤ ZCLPMAXR < 2¹⁵.
ZSATVMINR retains its value at a reset.
Note: For details on the setting range, see (2) 4 × 4 Matrix Operation, to (5) Coordinate
Transformation Flow and Saturation Processing, in section 23.1.2, Basic Functions.
Rev. 1.00 Nov. 22, 2007 Page 1219 of 1692
REJ09B0360-0100