SH7764 Datasheet, PDF (453/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
Table 12.11 DMA Transfer Matrix in On-Chip Peripheral module Request Mode*²
Transfer Destination
Transfer Source
MCU Space
On-Chip Peripheral
Module*¹
IL Memory
MCU space
No
Yes
No
On-chip peripheral
Yes
Yes
Yes
module*¹
IL memory
No
Yes
No
[Legend]
Yes: Transfer is available.
No: Transfer is not available.
Notes: 1. When the transfer source or the destination is an on-chip peripheral module, the
transfer size should be the same value of its register access size.
2. The transfer source or the transfer destination should be a register of request source in
on-chip peripheral module request mode. This transfer is available only cycle steal
mode.
(4) Bus Mode and Channel Priority
When the priority is set in fixed mode (CH0 > CH1) and channel 1 is transferring in burst mode, if
there is a transfer request to channel 0 with a higher priority, the transfer of channel 0 will begin
immediately.
At this time, if channel 0 is also operating in burst mode, the channel 1 transfer will continue after
the channel 0 transfer has completely finished.
When channel 0 is in cycle steal mode, channel 0 with a higher priority performs the transfer of
one transfer unit and the channel 1 transfer is continuously performed without releasing the bus
mastership. The bus mastership will then switch between the two in the order channel 0, channel
1, channel 0, and channel 1. In the bus status, the CPU cycle after data transfer in cycle steal mode
is replaced with data transfer in burst mode. (Hereinafter, this bus status is referred to as burst
mode prioritized execution.)
This example is shown in figure 12.10. When multiple channels are operating in burst modes, the
channel with the highest priority is executed first.
When DMA transfer is executed in the multiple channels, the bus mastership will not be given to
the bus master until all competing burst transfers are complete.
Rev. 1.00 Nov. 22, 2007 Page 397 of 1692
REJ09B0360-0100