SH7764 Datasheet, PDF (842/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
20.3 Operation
The E-DMAC, connected to the EtherC, allows efficient transfer of transmit/receive data between
the EtherC and memory (buffers) without CPU intervention. The E-DMAC automatically reads
the control information referred to as descriptors. The descriptors corresponding to each buffer
hold buffer pointers and other information. The E-DMAC reads transmit data from the transmit
buffer and writes receive data to the receive buffer according to the control information. By
arranging such multiple descriptors continuously (i.e., making a descriptor list), continuous
transmission or reception is possible.
20.3.1 Descriptor Lists and Data Buffers
By the communication program, a transmit descriptor list and a receive descriptor list should be
created in memory space prior to transmission and reception. The start addresses of these lists
should be set to the transmit descriptor list start address register and receive descriptor list start
address register.
The start addresses of the descriptor lists should be placed on the address boundaries in
accordance with the descriptor length specified by the E-DMAC mode register (EDMR). Here, the
start address of the transmit buffer can be placed on a longword, word, or byte boundary.
(1) Transmit Descriptor
Figure 20.2 shows the relationship between a transmit descriptor and a transmit buffer. The
descriptor can relate one transmit frame to one transmit buffer (single-frame/single-buffer
operation) or multiple transmit buffers (single-frame/multi-buffer operation).
When the transmit buffer length (TBL) is to be set to 1 to 16 bytes, the buffer address needs to be
placed on a 32-byte boundary. When the transmit buffer length (TBL) is set to 0 byte, operation
cannot be guaranteed.
Rev. 1.00 Nov. 22, 2007 Page 786 of 1692
REJ09B0360-0100