SH7764 Datasheet, PDF (680/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Table 18.3 SSI_DMAC0 Register State in Each Operating Mode
Channel Register Name
0
DMA mode register 0
RDMA transfer source
address register 0
RDMA transfer word
count register 0
WDMA transfer
destination address
register 0
WDMA transfer word
count register 0
DMA control register 0
Transmit suspension
block counter 0
Transmit suspension
transfer data register 0
Block count source
register 0
Block counter 0
n-times block transfer
interrupt count source
register 0
n-times block counter 0
1
DMA mode register 1
RDMA transfer source
address register 1
RDMA transfer word
count register 1
WDMA transfer
destination address
register 1
WDMA transfer word
count register 1
DMA control register 1
Transmit suspension
block counter 1
Abbreviation
SSIDMMR0
SSIRDMADR0
Power-On Reset Sleep Standby
H'0000 0000
Retained Retained
H'0000 0000
Retained Retained
SSIRDMCNTR0 H'0000 0000
Retained Retained
SSIWDMADR0 H'0000 0000
Retained Retained
SSIWDMCNTR0 H'0000 0000
SSIDMCOR0 H'0000 0000
SSISTPBLCNT0 H'0000 0000
SSISTPDR0
H'0000 0000
SSIBLCNTSR0 H'0000 0000
SSIBLCNT0
H'0000 0000
SSIBLNCNTSR0 H'0000 0000
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
SSIBLNCNT0
SSIDMMR1
SSIRDMADR1
H'0000 0000
H'0000 0000
H'0000 0000
SSIRDMCNTR1 H'0000 0000
SSIWDMADR1 H'0000 0000
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
SSIWDMCNTR1 H'0000 0000
SSIDMCOR1 H'0000 0000
SSISTPBLCNT1 H'0000 0000
Retained Retained
Retained Retained
Retained Retained
Rev. 1.00 Nov. 22, 2007 Page 624 of 1692
REJ09B0360-0100