SH7764 Datasheet, PDF (873/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
Bit
Bit Name Initial Value R/W Description
10

1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
9 to 2 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1, 0
LNST[1:0] Undefined* R
USB Data Line Status Monitor
Indicates the status of the USB data bus lines (D+
and D-) as shown in table 21.6.
These bits should be read after setting DPRPU to 1
to notify connection when the function controller
function is selected; whereas after setting DRPD to 1
to enable pulling down the lines when the host
controller function is selected.
Note: * Depends on the DP and DM pin status.
Table 21.6 USB Data Bus Line Status
LNST[1]
LNST[0]
During Full-
During High-
During Chirp
Speed Operation Speed Operation Operation
0
0
SE0
Squelch
Squelch
0
1
J state
Not squelch
Chirp J
1
0
K state
Invalid
Chirp K
1
1
SE1
Invalid
Invalid
[Legend]
Chirp:
Squelch:
Not squelch:
Chirp J:
Chirp K:
The reset handshake protocol is being executed in high-speed operation enabled
state (the HSE bit in SYSCFG is set to 1).
SE0 or idle state
High-speed J state or high-speed K state
Chirp J state
Chirp K state
Rev. 1.00 Nov. 22, 2007 Page 817 of 1692
REJ09B0360-0100