SH7764 Datasheet, PDF (384/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
11.7.3 Burst Read
Figure 11.12 shows the burst read timing chart, in which it is assumed that data is 64 bits wide,
bank close mode is used, and the burst length is four.
CLKOUT
CKE
Bank
address
Precharge
-sel
Address
CSn
R/W
RAS
CAS
DQMn
D[63:0]
(read)
BS
DACKn
(Active-low)
Q0 Q1 Q2 Q3
⋅ Transfer size: 32 bytes
⋅ External bus: 64 bits wide
⋅ BL: 4 bursts
⋅ CL: 3
Figure 11.12 Basic SDRAM Interface Timing (1) Burst Read
Rev. 1.00 Nov. 22, 2007 Page 328 of 1692
REJ09B0360-0100