SH7764 Datasheet, PDF (521/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
13.6 Interrupt Response Time
Table 13.7 shows the interrupt response time, which is the interval from when an interrupt request
occurs until the interrupt exception handling is started and the start instruction of the exception
handling routine is fetched.
Table 13.7 Interrupt Response Time
Item
NMI
Priority determination time
5Bcyc +
2Pcyc
Wait time until the CPU finishes
the current sequence
Interval from when interrupt
exception handling begins
(saving SR and PC) until a SHwy
bus request is issued to fetch the
start instruction of the exception
handling routine
Response Total
time
(S + 10) Icyc
+ 1Scyc
+ 5Bcyc
+ 2Pcyc
Minimum
29Icyc
+ SxIcyc
[Legend]
Icyc: Period for one CPU clock cycle
Scyc: Period for one SHwy clock cycle
Bcyc: Period for one bus clock cycle
Pcyc: Period for one peripheral clock cycle
S: Number of instruction execution states
Number of States
Peripheral Module
Other than
IRQ
GPIO
GPIO
4Bcyc +
2Pcyc
5Pcyc
7Pcyc
S-1 (≥ 0)
× Icyc
11Icyc
+ 1Scyc
Remarks
(S + 10) Icyc
+ 1Scyc
+ 4Bcyc
+ 2Pcyc
35Icyc
+ SxIcyc
(S + 10) Icyc
+ 1Scyc
+ 5Pcyc
31Icyc
+ SxIcyc*
(S + 10) Icyc
+ 1Scyc
+ 7Pcyc
39Icyc+
SxIcyc*
When
Icyc:Scyc:
Bcyc:Pcyc
= 4:2:1:1
Rev. 1.00 Nov. 22, 2007 Page 465 of 1692
REJ09B0360-0100