SH7764 Datasheet, PDF (397/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
Level 0
Level 1 _LCDC
Level 2
Super-
Hyway
Level 3
LCDC
SDRAM
control
VDC2
layer 1
VDC2
layer 2
Sub-round-robin
scheduling
VDC2
VDC2
layer 4
layer 3
G2D
data
Sub-round-robin
G2D ^scheduling
command
ATAPI
Figure 11.20 Arbitration of Access Requests (1)
Level 0
Level 1 _LCDC
Level 2
Super-
Hyway
LCDC
Level 3
Super-
Hyway
LCDC
SDRAM
control
VDC2
layer 1
VDC2
layer 2
Sub-round-robin
scheduling
VDC2
VDC2
layer 4
layer 3
G2D
data
Sub-round-robin
scheduling
G2D
command
ATAPI
G2D
data
Sub-round-robin
scheduling
G2D
command
ATAPI
Figure 11.21 Arbitration of Access Requests (2)
Rev. 1.00 Nov. 22, 2007 Page 341 of 1692
REJ09B0360-0100