SH7764 Datasheet, PDF (574/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 15 Serial Communication Interface with FIFO (SCIF)
Table 15.9 Maximum Bit Rates with External Clock Input
(Clock Synchronous Mode, t_Scyc = 12t_pcyc)
Pch (MHz)
External Input Clock (MHz) Maximum Bit Rate (bits/s)
45
3.7500
3750000.0
50
4.1666
4166666.6
54
4.5000
4500000.0
15.3.9 FIFO Control Register (SCFCR)
SCFCR resets the quantity of data in the transmit and receive FIFO data registers, sets the trigger
data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and
written to by the CPU.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
RSTRG[2:0]
RTRG[1:0]
TTRG[1:0]
MCE TFRST RFRST LOOP
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
15 to 11 —
Initial
Value
All 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 518 of 1692
REJ09B0360-0100