SH7764 Datasheet, PDF (1399/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 27 General Purpose I/O (GPIO)
Table 27.2 Multiplexed Pins Controlled by Pin Select Registers
Register
PTSEL_K
PTSEL_P
PTSEL_R
Bit
PTSEL_K7
[1:0]
PTSEL_K6
[1:0]
PTSEL_K5
PTSEL_K4
[1:0]
PTSEL_K3
[1:0]
PTSEL_K2
[1:0]
PTSEL_K1
[1:0]
PTSEL_K0
[1:0]
PTSEL_P11
PTSEL_P10
PTSEL_P9
PTSEL_P8
PTSEL_R15
PTSEL_R14
PTSEL_R13
PTSEL_R12
PTSEL_R11
Function 1
Function 2
Function 3
Function 4
WDTOVF output
(SYSTEM)
IRQ1 input (INT)
AUDCK output
(AUD)
DACK1 output
(DMAC)
SCK0 input/output AUDSYNC output FCLE output

(SCIF)
(AUD)
(FLCTL)
SCK1 input/output FR/B input (FLCTL) 

(SCIF)
LCD_DATA0 output DB0 output (VDC2) BT_DATA0 output 
(LCDC)
(VDC2)
LCD_CL1 output
(LCDC)
HSYNC/SPL*
BT_HSYNC output 
input/output (VDC2) (VDC2)
LCD_CLK input
DCLKIN input


(LCDC)
(VDC2)
LCD_FLM output
(LCDC)
VSYNC/SPS*
BT_VSYNC output
input/output (VDC2) (VDC2)
LCD_M_DISP
output (LCDC)
DE_H/DE_C output BT_DE_C output
(VDC2)
(VDC2)
RXD0 input (SCIF) AUDATA0 output 

(AUD)
TXD0 output (SCIF) AUDATA1 output 

(AUD)
RXD1 input (SCIF) AUDATA2 output 

(AUD)
TXD1 output (SCIF) AUDATA3 output 

(AUD)
D63 input/output IDED1 input/output 

(DATA)
(ATAPI)
D62 input/output IDED0 input/output 

(DATA)
(ATAPI)
D61 input/output IDED3 input/output 

(DATA)
(ATAPI)
D60 input/output IDED2 input/output 

(DATA)
(ATAPI)
D59 input/output IDED5 input/output 

(DATA)
(ATAPI)
Rev. 1.00 Nov. 22, 2007 Page 1343 of 1692
REJ09B0360-0100