SH7764 Datasheet, PDF (704/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Bit
6 to 4
3
Initial
Bit Name Value R/W
SCKS[2:0] 000
R/W

0
R
Description
• In SSIDMCOR4:
000: The SSI_CH4 audio clock = AUDIO_CLK4 is
input.
001: The SSI_CH4 audio clock = AUDIO_CLK5 is
input.
010: Setting prohibited
011: The SSI_CH4 audio clock = AUDIO_CLK0 is
input.
100: The SSI_CH4 audio clock = AUDIO_CLK1 is
input.
101: The SSI_CH4 audio clock = AUDIO_CLK2 is
input.
110: Setting prohibited
111: The SSI_CH4 audio clock = AUDIO_CLK3 is
input.
• In SSIDMCOR5:
000: The SSI_CH5 audio clock = AUDIO_CLK5 is
input.
001: Setting prohibited
010: The SSI_CH5 audio clock = AUDIO_CLK0 is
input.
011: The SSI_CH5 audio clock = AUDIO_CLK1 is
input.
100: The SSI_CH5 audio clock = AUDIO_CLK2 is
input.
101: Setting prohibited
110: The SSI_CH5 audio clock = AUDIO_CLK3 is
input.
111: The SSI_CH5 audio clock = AUDIO_CLK4 is
input.
Reserved
This bit is always read as an undefined value. The write
value should always be 0.
Rev. 1.00 Nov. 22, 2007 Page 648 of 1692
REJ09B0360-0100