SH7764 Datasheet, PDF (1212/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 G2D
• SS = 0 and REL = 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OP CODE = 1010_0010
Reserve (all 0)
Draw Mode
Reserve (all 0)
0 0 0 00 0 0 0
ROP
Sign extended Sign
Base Address (longword address)
00
0000
LW (0 ≤ LW ≤ 4087)
0000
RW (0 ≤ RW ≤ 4087)
0000
TH (0 ≤ TH ≤ 4094)
0000
BH (0 ≤ BH ≤ 4094)
Sign
BXC (-32768 ≤ BXC ≤ 32767)
Sign
BYC (-32768 ≤ BYC ≤ 32767)
Notes: 1. 8 ≤ LW + RW + 1 ≤ 4088 (multiple of 8), 1 ≤ TH + BH + 1 ≤ 4095
2. −32768 ≤ BXC − LW ≤ 32767, −32768 ≤ BYC − TH ≤ 32767, −32768 ≤ BXC + RW ≤
32767, −32768 ≤ BYC + BH ≤ 32767
3. Adding the address (longword: 32-bit units) where the command code is located to the
Base Address (longword: 32-bit units) must result in a quad word address (64-bit units).
1. Code
B'10100010
2. Rendering Attributes
Multi-Valued
Source
O
Reference Data
Specified
Binary Source Binary Work Color
O
(only WORK = 1)
Drawing Destination
Rendering
O
Work
Draw Mode
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1
MTRE Fixed CLIP RCLIP STRANS DTRANS WORK SS
to 0
REL COOF αE SRCDIRX SRCDIRY DSTDIRX DSTDIRY
b0
SαE
Rev. 1.00 Nov. 22, 2007 Page 1156 of 1692
REJ09B0360-0100