SH7764 Datasheet, PDF (363/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
11.5 Operation
11.5.1 Endian/Access Size and Data Alignment
This LSI supports both big-endian mode, in which the upper byte (MSByte) in a string of byte
data is at address 0, and little-endian mode, in which the lower byte (LSByte) in a string of byte
data is at address 0. The mode is specified by the external pin (MODE5 pin) at a power-on reset
through the RESET pin. At a power-on reset by PRESET, big-endian mode is specified when the
MD5 pin is low, and little-endian mode is specified when the MD5 pin is high.
A data bus width of 8, 16, or 32 bits can be selected for the normal memory interface (areas 0
and 3), and one of 32 or 64 bits can be selected for the SDRAM interface (areas 1 and 2). Data
alignment is carried out according to the data bus width and endian mode of each device.
Accordingly, when the data bus width is smaller than the access size, multiple bus cycles are
automatically generated to reach the access size. In this case, access is performed by incrementing
the addresses corresponding to the bus width. For example, when a longword access is performed
at the area with an 8-bit width in the SRAM interface, each address is incremented one by one,
and then access is performed four times. In the 32-byte transfer, a total of 32-byte data is
continuously transferred according to the set bus width. The first access is performed on the data
for which there was an access request, and the remaining accesses are performed in wrap around
method according to the set bus width. The bus is not released during these transfers. In this LSI,
data alignment and data length conversion between different interfaces is performed
automatically. (The accesses from the pixel bus and LCDC are not performed in the wrap around
method.)
Rev. 1.00 Nov. 22, 2007 Page 307 of 1692
REJ09B0360-0100