SH7764 Datasheet, PDF (1284/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
Panel clock
Internal Hsync
HSYNC
DEH
Display area
Internal Hsync
DEV
DEH
DEC
Note: The DEC signal is obtained by logically ANDing DEV and DEH (when DEC_MODE = 0 in SGMODE).
The CDE signal is asserted when the graphic data matches the chroma-key target color specified in CDECRKY.
Figure 24.3 Format 1 (Vsync, Hsync, DEV, DEH, DEC, and CDE Output)
Rev. 1.00 Nov. 22, 2007 Page 1228 of 1692
REJ09B0360-0100