SH7764 Datasheet, PDF (1018/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
Register
Name
Bit Name
DCPCTR ACLRM
PIPEnCTR
SQCLR
SQSET
SQMON
PBUSY
PID
PIPEnTRE TRENB
TRCLR
PIPEnTRN TRNCNT
Setting
Contents
Remarks
Auto buffer clear PIPE1 to PIPE9: Can be set
Sequence clear Clears the data toggle bit
Sequence set Sets the data toggle bit
Sequence
monitor
Monitors the data toggle bit
Pipe busy status
Response PID See section 21.4.3 (6), Response PID
Transaction
PIPE1 to PIPE5: Can be set
counter enable
Current
transaction
counter clear
PIPE1 to PIPE5: Can be set
Transaction
counter
PIPE1 to PIPE5: Can be set
(1) Pipe control register switching procedures
The following bits in the pipe control registers can be modified only when USB communication is
disabled (PID = NAK):
Registers that Should Not be Set in the USB Communication Enabled (PID = BUF) State
• Bits in DCPCFG and DCPMAXP
• The SQCLR and SQSET bits in DCPCTR
• Bits in PIPECFG, PIPEBUF, PIPEMAXP and PIPEPERI
• The ATREPM, ACLRM, SQCLR and SQSET bits in PIPExCTR
• Bits in PIPExTRE and PIPExTRN
In order to modify the above bits from the USB communication enabled (PID = BUF) state, follow
the procedure shown below:
1. Generate a bit modification request with the pipe control register.
2. Modify the PID corresponding to the pipe to NAK.
3. Wait until the corresponding CSSTS bit is cleared to 0 (only when the host controller function
has been selected).
4. Wait until the corresponding PBUSY bit is cleared to 0.
Rev. 1.00 Nov. 22, 2007 Page 962 of 1692
REJ09B0360-0100