SH7764 Datasheet, PDF (1096/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 22 LCD Controller (LCDC)
When the value in PALDnn[7:3] is 0, 0s should be written to PALDnn[2:0]. Then 8 bits are
extended.
22.4.3 Data Format
1. Packed 1bpp (Pixel Alignment in Byte is Big Endian) [Windows CE Recommended Format]
Address
+00
+01
+02
+03
…
+LAO+00
+LAO+01
+LAO+02
+LAO+03
…
MSB
LSB
7 6 5 4 3 2 1 0 [Bit]
P00 P01 P02 P03 P04 P05 P06 P07 (Byte0)
P08
(Byte1)
…
P10 P11 P12 P13 P14 P15 P16 P17
P18
…
Display Memory
↓ Top Left Pixel
P00 P01 P02 P03 P04 P05 P06 P07 ^…
P10 P11 P12 P13 P14 P15 P16 P17 ^…
…
…
Display
Pn: Put 1-bit data
LAO: Line Address Offset
—Unused bits should be 0
2. Packed 2bpp (Pixel Alignment in Byte is Big Endian) [Windows CE Recommended Format]
Address
+00
+01
+02
+03
…
+LAO+00
+LAO+01
+LAO+02
+LAO+03
…
MSB
76
P00
P04
54
P01
P05
32
P02
P06
…
P10 P11 P12
P14 P15 P16
…
Display Memory
LSB
1 0 [Bit]
P03 (Byte0)
P07 (Byte1)
P13
P17
↓ Top Left Pixel
P00 P01 P02 P03 P04 P05 P06 P07 ^…
P10 P11 P12 P13 P14 P15 P16 P17 ^…
…
…
Display
Pn=Pn[1:0]: Put 2-bit data
LAO: Line Address Offset
—Unused bits should be 0
3. Packed 4bpp (Pixel Alignment in Byte is Big Endian) [Windows CE Recommended Format]
Address
+00
+01
+02
+03
…
+LAO+00
+LAO+01
+LAO+02
+LAO+03
…
MSB
LSB
7 6 5 4 3 2 1 0 [Bit]
P00
P01
(Byte0)
P02
P03
(Byte1)
P04
P05
(Byte2)
…
P10
P11
P12
P13
P14
P15
…
Display Memory
↓ Top Left Pixel
P00 P01 P02 P03 P04 P05 P06 P07 ^…
P10 P11 P12 P13 P14 P15 P16 P17 ^…
…
…
Display
Pn=Pn[3:0]: Put 4-bit data
LAO: Line Address Offset
—Unused bits should be 0
Rev. 1.00 Nov. 22, 2007 Page 1040 of 1692
REJ09B0360-0100