SH7764 Datasheet, PDF (749/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
(b) Transmission using Interrupt Data Flow Control
Start
Release reset,
specify configuration bits
in SSICR
Enable SSI module,
enable data interrupt,
enable error interrupt
For n =
( (CHNL + 1) x 2)
Loop
Wait for interrupt
from SSI
Data interrupt?
No
Yes
Load data of channel n
Specify TRMD, EN, SCKD,
SWSD, MUEN, DEL, PDTA,
SDTA, SPDP, SWSP, SCKP,
SWL, DWL, CHNL
EN = 1,
DIEN = 1,
UIEN = 1, OIEN = 1
Use SSI status register bits
to realign data
after underflow/overflow
Next Channel
Yes
More data
to be send?
No
Disable SSI module,
disable data interrupt,
disable error interrupt,
enable Idle interrupt
EN = 0,
DIEN = 0
UIEN = 0, OIEN = 0,
IIEN = 1
Wait for idle interrupt
from SSI module
Reset SSI module if required
End
Figure 18.20 Transmission Using Interrupt Data Flow Control
Rev. 1.00 Nov. 22, 2007 Page 693 of 1692
REJ09B0360-0100