SH7764 Datasheet, PDF (760/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 19 Ethernet Controller (EtherC)
Name
Abbreviation R/W
P4 Address
Area 7
Address
Access
Size
Random number generation counter
upper limit setting register
RDMLR
R/W H'FEF0 0140 H'1EF0 0140 32
PAUSE Frame Receive Counter Register RFCF
R
H'FEF0 0160 H'1EF0 0160 32
PAUSE frame retransmit counter register TPAUSECR R
H'FEF0 0168 H'1EF0 0168 32
Broadcast frame receive count setting
register
BCFRR
R/W H'FEF0 016C H'1EF0 016C 32
Note: * P4 is the address when virtual address space P4 area is used. Area 7 is the address
when physical address space area 7 is accessed by using the TLB.
Table 19.3 Register States in Each Operation Mode
Name
EtherC mode register
EtherC status register
EtherC interrupt permission register
Receive frame length register
PHY interface register
MAC address high register
MAC address low register
PHY status register
Transmit retry over counter register
Delayed collision detect counter register
Lost carrier counter register
Carrier not detect counter register
CRC error frame receive counter register
Frame receive error counter register
Too-short frame receive counter register
Too-long frame receive counter register
Residual-bit frame receive counter register
Multicast address frame receive counter register
IPG register
Automatic PAUSE frame register
Manual PAUSE frame register
Abbreviation
ECMR
ECSR
ECSIPR
RFLR
PIR
MAHR
MALR
PSR
TROCR
CDCR
LCCR
CNDCR
CEFCR
FRECR
TSFRCR
TLFRCR
RFCR
MAFCR
IPGR
APR
MPR
Software Reset
Initialised
Initialised
Initialised
Initialised
Initialised
Initialised
Initialised
Initialised
Initialised
Initialised
Initialised
Initialised
Initialised
Initialised
Initialised
Initialised
Initialised
Initialised
Initialised
Initialised
Initialised
Rev. 1.00 Nov. 22, 2007 Page 704 of 1692
REJ09B0360-0100