SH7764 Datasheet, PDF (1599/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 32 List of Registers
Module
Register Name
P4 Area
Abbreviation R/W Address
Area 7
Address
Register
Access
Size* Remarks
ATAPI
ATAPI status
ATAPI_STATU R/W H'FFF0 0084
32
S
Interrupt enable
ATAPI_INT_EN R/W H'FFF0 0088
32
ABLE
PIO timing
ATAPI_PIO_TI R/W H'FFF0 008C
32
MING
Multiword DMA timing ATAPI_MULTI_ R/W H'FFF0 0090
32
TIMING
Ultra DMA timing
ATAPI_ULTRA_ R/W H'FFF0 0094
32
TIMING
Descriptor table base ATAPI_DTB_A R/W H'FFF0 0098
32
address
DR
DMA start address
ATAPI_DMA_ R/W H'FFF0 009C
32
START_ADR
DMA transfer count
ATAPI_DMA_ R/W H'FFF0 00A0
32
TRANS_CNT
ATAPI control 2
ATAPI_
R/W H'FFF0 00A4
32
CONTROL2
Reserved
R
H'FFF0 00A8
32
Reserved
R
H'FFF0 00AC
32
ATAPI signal status
ATAPI_SIG_ST R
H'FFF0 00B0
32
Byte swap
ATAPI_BYTE_ R/W H'FFF0 00BC
32
SWAP
Note: * The above registers should be accessed in longword units (32 bits); byte and word
accesses are prohibited.
Rev. 1.00 Nov. 22, 2007 Page 1543 of 1692
REJ09B0360-0100