SH7764 Datasheet, PDF (306/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 10 Clock Pulse Generator (CPG)
10.4 Register Descriptions
Table 10.3 shows the CPG register configuration. Table 10.4 shows the register states in each
operating mode.
Table 10.3 Register Configuration
Register Name
Abbreviation R/W
Frequency control register FRQCR
R
PLL control register
PLLCR
R/W
VDC2 clock control register VDC2CLKCR R/W
Area P4
Address
H'FFC8 0000
H'FFC8 0024
H'FFC8 0004
Area 7
Address
H'1FC8 0000
H'1FC8 0024
H'1FC8 0004
Access
Size
32
32
32
Table 10.4 Register States in Each Operating Mode
Register Name
Abbreviation
Power-On
Reset
Standby Sleep
Frequency control register
FRQCR
H'x032 0044* Retained Retained
PLL control register
PLLCR
H'0000 E001 Retained Retained
VDC2 clock control register
VDC2CLKCR H'0000 0080 Retained Retained
Note: * The initial value after a power-on reset is determined by the combination of the external
pins, MODE0, MODE1, and MODE2.
Rev. 1.00 Nov. 22, 2007 Page 250 of 1692
REJ09B0360-0100