SH7764 Datasheet, PDF (513/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
and determines the priorities of individual interrupt sources. The lowest one bit is then rounded
off, the data is converted to 4-bit data, and the priority levels are notified. For example, two
interrupt sources whose priority levels are set to H'1A and H'1B are both output as 4-bit priority
level H'D. That is, the two interrupt sources have the same value. However, in terms of the
INTEVT code that is notified when a conflict occurs between two interrupt sources, the INTEVT
code that corresponds to the interrupt with a priority level of H'1B has priority. This is because the
priority level of H'1B is higher than that of H'1A when comparing 5-bit data. When a conflict
occurs between interrupts with the same priority level, the INTEVT code is notified according to
the priority level shown in table 13.1.
INTC can distinguish H'1A from H'1B on-chip module
interrupt priority level that is same for the CPU.
INTC
Priority level: high (H'1B)
11011
low (H'1A)
11010
Priority level H'01 is same with interrupt request mask.
INTC
Priority level: H'01
00001
CPU
1101
1101
Priority level:
even (H'D)
CPU
0000
Priority level: H'0 (interrupt is masked)
When multiple interrupt requests from on-chip modules
occur simultaneously, the INTC processes the priority level
H'1B is higher than that of H'1A.
However, if an external interrupt request occurs too, then
the external interrupt request will be higher priority in some
case;
- NMI interrupt request
- IRQ interrupt request that has the same priority
level or more (H'D or more in this figure).
Priority level H'01 becomes to H'00 by rounding off the lowest
bit, and then the interrupt is not notified to the CPU. The
setting range of the interrupt priority register is H'02 to H'1F
(30 priority levels).
Figure 13.2 On-Chip Module Interrupt Priority
13.4.5 Interrupt Exception Handling and Priority
Table 13.6 lists the codes for the interrupt event register (INTEVT), and the order of interrupt
priority.
Each interrupt source is assigned a unique INTEVT code. The start address of the exception
handling routine is common to each interrupt source. Therefore, to identify the interrupt source,
branching is performed at the start of the exception handling routine using the INTEVT value. For
instance, the INTEVT value is used as a branch offset.
Rev. 1.00 Nov. 22, 2007 Page 457 of 1692
REJ09B0360-0100