SH7764 Datasheet, PDF (789/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 19 Ethernet Controller (EtherC)
19.3.25 PAUSE Frame Retransmit Counter Register (TPAUSECR)
PFTCR is a 16-bit counter that indicates the number of times a PAUSE frame is retransmitted.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
——
—
—
—
—
—
TXP[7:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit
31 to 8
Bit Name

7 to 0 TXP[7:0]
Initial
Value
All 0
All 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R PAUSE Frame Retransmit Count
Rev. 1.00 Nov. 22, 2007 Page 733 of 1692
REJ09B0360-0100