SH7764 Datasheet, PDF (755/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
register (SSIRDMCNTR) and the WDMA data transfer count register (SSIWDMCNTR)
should be read only the setting value.
• In the block count source register (SSIBLCNTSR), specify the number of byte that must be a
multiple of the maximum burst size number of the RDMA or WDMA
• The transmit suspension block counter (SSISTPBLCNT) and the transmit suspension transfer
data register (SSIWDMCNTR) are unable to be written in the conditions of the DMA is
transferring data.
• The RDMA data transfer count register (SSIRDMCNTR) and the WDMA data transfer count
register (SSIWDMCNTR) should be read only the setting value.
• Refer to the block counter register (SSIBLCNT) and the n-times block counter (SSIBLNCNT)
for the number of data transferring.
• The block counter register (SSIBLCNT) and the n-times block counter register (SSIBLNCNT)
are only readable and cleared by the software reset (DMRST). The transferred data count
timing for the conditions of implementing the transmit operations is when data transfer from
the transmit FIFO in the SSI_DMAC to the data buffers in the SSI and for the conditions of
implementing the receiving operation is when data transfer from the data buffers in the SSI to
the receive FIFO in the SSI_DMAC.
Rev. 1.00 Nov. 22, 2007 Page 699 of 1692
REJ09B0360-0100