SH7764 Datasheet, PDF (412/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
1 MB
boundary
2n MB
boundary
64 MB/area
UM space
8
LTAM[28:20] LTAD[28:20]
9
9
Linear address A[28:00]
9 7 4 45
1 MB
A maximum of
eight areas
can be defined
as tiled memory
areas
2ⁿ MB
1 MB minimum
9
9
LTGBM = 8 bits/pixel
MWX = 512 pixels
1
8
1
44
Tiled memory address B[28:00]
Figure 11.27 Operation of Linear-to-Tiled Memory Address Translation
Rev. 1.00 Nov. 22, 2007 Page 356 of 1692
REJ09B0360-0100