SH7764 Datasheet, PDF (654/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 ATAPI
IDEIORD/
IDEIOWR
DCT
ATA address
DST
DPW
DST
DCT: Cycle setting
DPW: Setting the low pulse width for IDEIORD/IDEIOWR
DST: Setting the setup time for the address and IDEIORD/IDEIOWR
Note: The prefix pS means slave and the prefix pM means master. DCT, DST, and DPW are set by multiplying the setting of each
register by the cycle of the Pixcelclk.
Figure 17.2 PIO Timing Register
PIO timing register value table (Master / Slave)
Pixel Bus Clock
100 MHz
Mode 0
H'3DF0
Mode 1
H'28F6
Mode 2
H'22F4
Mode 3
H'134C
Mode 4
H'0D44
17.3.5 Multiword DMA Timing Register (ATAPI_MULTI_TIMING)
Set the machine cycle numbers to the following bits in this register before access to the ATAPI
device.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
mSDCT
mSDPW
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
mMDCT
mMDPW
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
31 to 27 —
All 0
26 to 21 mSDCT 0
20 to 16 mSDPW 0
R/W Description
R
Reserved
R/W mSDCT sets the cycle time of the Slave ATAPI device.
R/W mSDPW sets the IDEIORD/IDEIOWR pulse width of
the Slave ATAPI device.
Rev. 1.00 Nov. 22, 2007 Page 598 of 1692
REJ09B0360-0100