SH7764 Datasheet, PDF (1308/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.6.11 Chroma-Key Color Registers (GROPCRKY1_2 to GROPCRKY1_4)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16








ALPHA[7:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
R/W: R/W
0
R/W
R[4:0]
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
G[5:0]
0
0
R/W R/W
0
R/W
0
R/W
0
R/W
0
R/W
B[4:0]
0
R/W
0
R/W
0
R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 24 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
23 to 16 ALPHA[7:0] H'00
R/W These bits specify the α value after replacement.
15 to 11 R[4:0]
00000
R/W
These bits specify the R value after replacement.
10 to 5 G[5:0]
000000 R/W These bits specify the G value after replacement.
4 to 0 B[4:0]
00000
R/W
These bits specify the B value after replacement.
Note: Layer 1 is the bottom image which has no α control target, so the above settings are
prohibited for layer 1.
Each register specifies a set of color information to replace the color that matches the chroma-key
target RGB values.
α calculation is done as follows.
Output R = R (current graphic image) × α + R (lower-layer graphic image) × (1 - α)
Output G = G (current graphic image) × α + G (lower-layer graphic image) × (1 - α)
Output B = B (current graphic image) × α + B (lower-layer graphic image) × (1 - α)
Rev. 1.00 Nov. 22, 2007 Page 1252 of 1692
REJ09B0360-0100