SH7764 Datasheet, PDF (689/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
18.3.1 DMA Mode Registers 0 to 5 (SSIDMMR0 to SSIDMMR5)
SSIDMMR0 to SSIDMMR5 is a 32-bit readable/writable register that set the operation mode for
SSI_DMAC other than the port function. This register value is initialized when either of the
conditions is implemented such as hardware reset, software reset or software reset for SSI_DMAC
(DMRST bit in SSIDMACOR0 to SSIDMACOR3).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16













RDS
AM

WDD
AM
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R R/W R R/W
Bit: 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0







 RDMBSZ[1:0] WDMBSZ[1:0] 



Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R
R
R
R
Initial
Bit
Bit Name Value R/W Description
31 to 19 
All 0 R
Reserved
These bits are always read as a 0. The write value
should always be 0.
18
RDSAM 0
R/W RDMA Transfer Source Address Mode
Increments or decrements the transfer source address
during RDMA transfer.
0: Increments the transfer source address (+4).
1: Decrements the transfer source address (–4).
17

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
16
WDDAM 0
R/W WDMA Transfer Destination Address Mode
Increments or decrements the transfer destination
address during WDMA transfer.
0: Increments the transfer destination address (+4).
1: Decrements the transfer destination address (–4).
15 to 8 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 633 of 1692
REJ09B0360-0100