SH7764 Datasheet, PDF (1260/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 G2D
• Source pixel format is RGB = 565 (SPF = 0)
Bit
23 to 19
15 to 10
7 to 3
Name
COR (Color offset R)
COG (Color offset G)
COB (Color offset B)
Description
Color offset red component
Color offset green component
Color offset blue component
Bits 18 to 16, 9, 8, and 2 to 0 are discarded. These bits are always read as 0.
• Source pixel format is ARGB = 1555 (SPF = 1)
Bit
23 to 19
15 to 11
7 to 3
Name
COR (Color offset R)
COG (Color offset G)
COB (Color offset B)
Description
Color offset red component
Color offset green component
Color offset blue component
Bits 18 to 16, 10 to 8, and 2 to 0 are discarded. These bits are always read as 0.
Bits 31 to 24—Reserved: The write value should always be 0. These bits are always read as 0.
23.3.4 Rendering Control Registers
(1) Rendering Control Register (RCLR)
Offset:
H'0C0
Initial Value: H'00000000
The rendering control register (RCLR) is a 32-bit readable/writable register which specifies the
rendering attributes.
Bit 25—Source Transparent Color Polarity (STP): Selects whether source transparency occurs
when the source data and the value set in the source transparent color register (STCR) match or do
not match.
Bit 25: STP
0
1
Description
Source transparency at a match (Initial value)
Source transparency at a mismatch
Rev. 1.00 Nov. 22, 2007 Page 1204 of 1692
REJ09B0360-0100