SH7764 Datasheet, PDF (413/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
11.12 Usage Notes
11.12.1 Refresh
In refresh standby mode and hardware standby mode, auto-refresh is unavailable. For the memory
system requiring refresh operation, it is necessary to put the memory into the self-refresh state
prior to transition to refresh standby mode. In hardware standby mode, neither self-refresh nor
auto-refresh is available because all the pins are driven to the high-impedance state.
11.12.2 External Bus Arbitration
In refresh standby mode, the bus mastership is not released. For the system that carries out
external bus arbitration, it is necessary to set the BREQ enable bit (BREQEN in BCR) to 0 prior to
transition to refresh standby mode. If transition is made to refresh standby mode with the BREQ
enable bit set to 1, correct operation is not guaranteed.
Rev. 1.00 Nov. 22, 2007 Page 357 of 1692
REJ09B0360-0100