SH7764 Datasheet, PDF (442/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
(3) On-Chip Peripheral Module Request Mode
In this mode, a transfer is performed at the transfer request signal of an on-chip peripheral module.
Transfer request signals comprise the transmit data empty transfer request and receive data full
transfer request from the SCIF0 to SCIF2, USB, FLCTL and SRC set by DMARS0/1/2.
When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0,
NMIF = 0), a transfer is performed upon the input of a transfer request signal.
When a transmit data empty transfer request of the SCIF0 is set as the transfer request, the transfer
destination must be the SCIF0's transmit data register. Likewise, when receive data full transfer
request of the SCIF0 is set as the transfer request, the transfer source must be the SCIF0's receive
data register. These conditions also apply to the SCIF1, SCIF2, USB, FLCTL and SRC.
Table 12.8 Selecting On-Chip Peripheral Module Request Modes with Bits RS[3:0]
CHCR
RS[3:0]
1000
DMARS
MID
RID
001000 01
10
001010 01
10
010000 01
10
010001 01
DMA Transfer
Request
DMA Transfer
Source
Request Signal
Source
SCI F0
TXI (transmit FIFO data
Any
transmitter empty interrupt)
SCIF0
receiver
RXI (receive FIFO data
full interrupt)
SCFRDR0
SCI F1
TXI (transmit FIFO data
Any
transmitter empty interrupt)
SCIF1
receiver
RXI (receive FIFO data
full interrupt)
SCFRDR1
SCIF2
TXI (transmit FIFO data
Any
transmitter empty interrupt)
SCIF2
receiver
RXI (receive FIFO data full SCFRDR2
interrupt)
USB
Transmit data empty request Any
transmitter*
USB
receiver*
Receive data is not read
USB
D1FIFO
10 USB
Transmit data empty request Any
transmitter*
USB
receiver*
Receive data full request
USB
D0FIFO
Bus
Destination Mode
SCFTDR0 Cycle
steal
Any
Cycle
steal
SCFTDR1 Cycle
steal
Any
Cycle
steal
SCFTDR2 Cycle
steal
Any
Cycle
steal
USB
D1FIFO
Cycle
steal/
burst
Any
Cycle
steal/
burst
USB
D0FIFO
Cycle
steal/
burst
Any
Cycle
steal/
burst
Rev. 1.00 Nov. 22, 2007 Page 386 of 1692
REJ09B0360-0100