SH7764 Datasheet, PDF (712/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Initial
Bit
Bit Name Value R/W Description
1, 0
PR[1:0]
All 0 R/W Priority Modes 1, 0
These bits set the priority when multiple transfer
requests from SSIs (SSI_CH0 to SSI_CH5) occur
simultaneously.
00: SSI_CH0 > SSI_CH1 > SSI_CH2 (SSI_CH3 >
SSI_CH4 > SSI_CH5)
01: SSI_CH0 > SSI_CH2 > SSI_CH1 (SSI_CH3 >
SSI_CH5 > SSI_CH4)
10: Setting prohibited
11: Round robin of SSI_CH0 to SSI_CH2 (Round robin
of SSI_CH3 to SSI_CH5)
Note: Descriptions within parenthesis "( )" indicate those for SSIDMAOR1.
18.3.14 Interrupt Status Registers 0 and 1 (SSIDMINTSR0 and SSIDMINTSR1)
SSIDMINTSR0 and SSIDMINTSR1 are 32-bit readable/writable registers that indicate the
interrupt sources of SSI_DMAC0/1. Interrupts enabled by the interrupt mask registers
(SSIDMINTMR0 and SSIDMINTMR1) will occur other than the port function. Each bit in
SSIDMINTSR0 and SSIDMINTSR1 is cleared to 0 by writing 1 to it. Writing 0 to it is ignored.
This register value is initialized when either of the conditions is implemented such as hardware
reset, software reset or software reset for SSI_DMAC (DMRST bit in SSIDMACOR0 to
SSIDMACOR3).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16











BLK BLKN DM TXFIFO RXFIFO
END2 END2 END2 FUL2 EMP2
Initial value: 0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
R/W: R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0



BLK BLKN DM TXFIFO RXFIFO
END1 END1 END1 FUL1 EMP1



BLK BLKN DM TXFIFO RXFIFO
END0 END0 END0 FUL0 EMP0
Initial value: 0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
R/W: R
R
R R/W R/W R/W R/W R/W R
R
R R/W R/W R/W R/W R/W
Rev. 1.00 Nov. 22, 2007 Page 656 of 1692
REJ09B0360-0100