SH7764 Datasheet, PDF (640/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 16 I²C Bus Interface
3. Set the master control register to H'8A
(Set the force stop control bit).
4. Reset the MDR bit.
(5) Wait for End of Reception
1. Handle the receive interrupt (MDR) in the last byte: that is, read the data and clear the MDR.
2. Wait for master event, MST in the master status register.
3. Reset the MST bit.
16.5.3 Master Transmitter - Restart - Master Receiver
In order to set up the master interface to transmit a data packet on the I²C bus, issue a restart, then
read byte data back from the slave, follow the following procedure:
(1) Load Clock Control Register
1. Set the SCL clock generation divider (SCGD) to H'03
(SCL frequency of 400 kHz).
2. Set the clock division (CDF) to H'2
(The peripheral clock is 50 MHz and the IIC's internal clock IICck is 16.7 MHz.)
(2) Load Master Control Register and Address
1. Set the master address register to address of slave being accessed and STM1 bit (writes mode:
0).
2. Set the master control register to H'89
(MDBS = 1, MIE = 1, ESG = 1).
(3) Wait for Outputting Address
1. Wait for master event (an interrupt of the MAT and MDE bits in the master status register).
2. Set the master address register to address of slave being accessed and STM1 bit (read mode:
1).
When the enable start generation bit in the master control register is still set, at the end of the
byte transmission the master will issue a restart. Since the new address has been loaded above
the bus direction will be changed.
3. Reset the MAT bit.
Rev. 1.00 Nov. 22, 2007 Page 584 of 1692
REJ09B0360-0100