SH7764 Datasheet, PDF (1653/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 33 Electrical Characteristics
CLKOUT
BANK
Precharge
Address
CSn
R/W
RAS
CAS
DQMn
D63 to D0
BS
CKE
DACKn
(Low-active)
DTENDn
(Low-active)
Tr
Trw Tc1 Tc2 Td1 Td2
tAD
BANK
tAD
Row
tAD
Row
tCSD
tAD
H
tAD
Col
tAD
tAD
tAD
tCSD
tRWD
tRASD ^tRASD
tCASD
tCASD tCASD
tDQMD
tBSD
tDQMD
tDQMD
tRDS
tRDH
d0
d1
d2
d3
tBSD tBSD
tCKED
tDACD
tDACD
tDACD
tDTED
tDTED
tDTED
Figure 33.18 SRAM Bus Cycle in Bank Close Mode Read Bus Cycle
(ACT-READA)
(BOMODE[1:0]= 1, SCL[2:0]= 000, SRCD= 0, IRP= 2cyc, CAS Latency= 2cyc)
Rev. 1.00 Nov. 22, 2007 Page 1597 of 1692
REJ09B0360-0100