SH7764 Datasheet, PDF (1472/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Power-Down Mode
Initial
Bit
Bit Name Value R/W Description
19
H-UDI
0
R/W H-UDI Module Stop Bit
When set to 1, the clock supply to the H-UDI module is
halted.
0: H-UDI operates
1: Clock supply to H-UDI is halted
18

0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
17
UBC
0
R/W UBC Module Stop Bit
When set to 1, the clock supply to the UBC module is
halted.
0: UBC operates
1: Clock supply to UBC is halted
16

0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
15
LCDC
0
R/W LCDC Module Stop Bit
When set to 1, the clock supply to the LCDC module is
halted.
0: LCDC operates
1: Clock supply to LCDC is halted
14

0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
13
TMU
0
R/W TMU Module Stop Bit
When set to 1, the clock supply to the TMU module is
halted.
0: TMU operates
1: Clock supply to TMU is halted
12
FLCTL 0
R/W FLCTL Module Stop Bit
When set to 1, the clock supply to the FLCTL module is
halted.
0: FLCTL operates
1: Clock supply to FLCTL is halted
Rev. 1.00 Nov. 22, 2007 Page 1416 of 1692
REJ09B0360-0100