SH7764 Datasheet, PDF (319/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
11.4 Register Description
Table 11.5 shows the MCU registers. The registers are 64 bits wide, but they should be accessed
in longword (32-bit) units. When data is written, it is reflected in the state in longword units.
When data is read, a longword value set at the point of access is referenced. When accessing data
in bits 63 to 32 and bits 31 to 0, specify the addresses 8n + 0 and 8n + 4, respectively. These
registers control the interface with various types of memories, and the number of wait states.
Table 11.5 Register Configuration
Address
H'FF800000
H'FF800008
H'FF800010
H'FF800018
H'FF800030
H'FFAxxxxx
H'FF800200
H'FF800100
H'FF800108
H'FF800110
H'FF800118
H'FF800120
H'FF800128
H'FF800130
Register Name
Abbr.
Version control register
VCR
Memory interface mode register MIM
SDRAM control register
SCR
SDRAM timing register
STR
SDRAM row attribute register SDRA
SDRAM mode register
SDMR
Arbitration mode register
AMR
Linear-to-tiled memory address LTC0
translation control register 0
Linear-to-tiled memory address LTAD0
translation area start address
register 0
Linear-to-tiled memory address LTAM0
translation area start address
mask register 0
Linear-to-tiled memory address LTC1
translation control register 1
Linear-to-tiled memory address LTAD1
translation area start address
register 1
Linear-to-tiled memory address LTAM1
translation area start address
mask register 1
Linear-to-tiled memory address LTC2
translation control register 2
Initial Value
Access
Size
H'0B04000000000000 32
H'00000000061A0x40 32
H'0000000000000000 32
H'0000000000FFFFE7 32
H'0000000000000200 32

32
H'0000000004000000 32
H'0000000000000000 32
H'0000000000000000 32
H'0000000000000000 32
H'0000000000000000 32
H'0000000000000000 32
H'0000000000000000 32
H'0000000000000000 32
Rev. 1.00 Nov. 22, 2007 Page 263 of 1692
REJ09B0360-0100