SH7764 Datasheet, PDF (783/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 19 Ethernet Controller (EtherC)
19.3.19 IPG Register (IPGR)
IPGR sets the IPG (Inter Packet Gap). This register must not be changed while the transmitting
and receiving functions of the EtherC mode register (ECMR) are enabled. (For details, refer to
section 19.4.6, Operation by IPG Setting.)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
IPG[4:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
R/W: R R R R R R R R R R R R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
R/W
31 to 5 
All 0
R
4 to 0
IPG[4:0] H'14
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Inter Packet Gap
Sets the IPG value every 4-bit time.
H'00: 16-bit time
H'01: 20-bit time
:
:
H'14: 96-bit time (Default)
:
:
H'1F: 140-bit time
Rev. 1.00 Nov. 22, 2007 Page 727 of 1692
REJ09B0360-0100