SH7764 Datasheet, PDF (810/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit
3 to 1
0
Bit Name

SWR
Initial
Value
All 0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Software Reset
[Writing]
0: Disabled
1: Internal hardware is reset. For the registers that are
reset, see tables 19.3 and 20.2.
20.2.2 E-DMAC Transmit Request Register (EDTRR)
EDTRR is a 32-bit readable/writable register that issues transmit directives to the E-DMAC. After
having transmitted one frame, the E-DMAC reads the next descriptor. If the transmit descriptor
valid bit in this descriptor is set (valid), the E-DMAC continues transmission. Otherwise, the E-
DMAC clears the TR bit and stops the transmit DMAC operation.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— TR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R/W
Bit
31 to 1
0
Initial
Bit Name Value

All 0
TR
0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Transmit Request
0: Transmission-halted state. Writing 0 does not stop
transmission. Termination of transmission is controlled
by the TACT bit of the transmit descriptor.
1: Transmit DMA operation being performed by the E-
DMAC. After writing 1 to this bit, the E-DMAC starts
reading a transmit descriptor.
Rev. 1.00 Nov. 22, 2007 Page 754 of 1692
REJ09B0360-0100