SH7764 Datasheet, PDF (222/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 7 Memory Management Unit (MMU)
7.2.6 Page Table Entry Assistance Register (PTEA)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
−
−
EPR
ESZ
−
−
−
−
Initial value: 0
0
−
−
−
−
−
−
−
−
−
−
0
0
0
0
R/W: R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R
Bit
31 to 14
13 to 8
7 to 4
3 to 0
Initial
Bit Name Value
R/W

All 0
R
EPR
ESZ
Undefined R/W
Undefined R/W

All 0
R
Description
Reserved
For details on reading/writing these bits, see General
Precautions on Handling of Product.
Page Control Information
Each bit has the same function as the corresponding
bit of the unified TLB (UTLB). For details, see section
7.4, TLB Functions (TLB Extended Mode; MMUCR.ME
= 1)
Reserved
For details on reading/writing these bits, see General
Precautions on Handling of Product.
Rev. 1.00 Nov. 22, 2007 Page 166 of 1692
REJ09B0360-0100