SH7764 Datasheet, PDF (1539/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 31 User Debugging Interface (H-UDI)
31.4.1 Instruction Register (SDIR)
SDIR is a 16-bit read-only register that can be read from the CPU. Commands are set via the serial
input (TDI). SDIR is initialized by TRST or in the Test-Logic-Reset state and can be written by
the H-UDI irrespective of the CPU mode. Operation is not guaranteed when a reserved command
is set to this register.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TI
Initial value: 0
0
0
0
1
1
1
0
1
1
1
1
1
1
1
1
R/W: R R R R R R R R R R R R R R R R
Bit
15 to 8
7 to 0
Bit Name Initial Value R/W Description
TI
0000 1110 R Test Instruction Bits 7 to 0
0110 xxxx : H-UDI reset negate
0111 xxxx : H-UDI reset assert
101x xxxx : H-UDI interrupt
0000 1110: Initial state
Other than above: Setting prohibited
Note: Though H-UDI reset asserted, CPG and WDT
registers are not initialized.

All 1
R Reserved
These bits are always read as 1.
Rev. 1.00 Nov. 22, 2007 Page 1483 of 1692
REJ09B0360-0100